The present invention relates generally to integrated circuit (IC) designs, and more particularly to a semiconductor structure for reducing a gate resistance while providing a self-aligned silicide contact for a static random access memory (SRAM) cell.
As the semiconductor technology advances into the deep sub-micron realm, semiconductor structures become ever more crowded in an IC chip. SRAM cells, for instance, have become so dense that it has become increasingly difficult to form all the necessary electrical wiring in a SRAM chip. The interconnection structure from one metal interconnection wiring level to another, and also into the source/drain, gate, and body of a metal-oxide-semiconductor (MOS) transistor, require vertical conductive vias. In dual damascene metallization, metal, typically copper, is filled into etched vias and trenches, and excess is polished off by a process, such as chemical-mechanical-polish (CMP). Metal-filled vias provide vertical connections and metal-filled trenches provide lateral pads and lines.
Vias are typically the smallest features that must be resolved by lithography and etching. A metal-filled via down from the metal 1 level to contacts on the active semiconductor substrate must be small enough to fit without causing an electrical short to any other substrate site, to a polycrystalline silicon (poly) line or gate, or to another via.
Two structures are often used to facilitate via formation down to a contact. The first is a silicide, a layer formed on top of a poly gate for providing an Ohm contact between the poly gate and via. The second is a self-aligned contact. Here, a cap layer is formed on the top surface of poly gates. In combination with spacers on the sidewalls of the poly gates, the cap layer fully insulates the poly gates on all sides. A metal layer is formed on source/drain regions of a semiconductor substrate. The semiconductor substrate is thermally treated to form silicide layers at the interfaces of the metal layer and the source/drain regions as self-aligned contacts. Due to the cap layer, the poly gate is protected from formation of silicide thereon during the thermal treatment process.
These two structures are rather mutually exclusive. If self-aligned contact is used, then the cap layer atop the poly gate prevents the formation of silicide on the poly gate. As a result, the poly gate is left with a resistance that is too high for proper circuit function.
Therefore, desirable in the art of integrated circuit designs are additional structures and methods for providing self-aligned silicide and self-aligned contacts in a simultaneous and effective fashion.